The present embodiments relate to electronic devices and circuits and are more particularly directed to a static random access memory (“SRAM”) with a temperature-dependent voltage control in its sleep mode.
Electronic circuits have become prevalent in numerous applications, including uses for devices in personal, business, and other environments. Demands of the marketplace affect many aspects of the design of these circuits, including factors such as device power consumption and cost of operation. Various of these electronic circuits include some aspect of digital signal processing and, quite often, these circuits include storage devices or memories. One type of popular memory is the SRAM. An SRAM has a static nature, that is, it does not require the data in each of its memory cells to be refreshed, which is required by way of contrast in a dynamic RAM (“DRAM”). Typically, the SRAM is also considered faster and more reliable than DRAM, and indeed it has found favor in numerous uses, including uses in cache memory.
With the prevalence of SRAM memory in numerous devices and applications, the SRAM also is subject to the above-introduced factors of power consumption and cost of operation. In this regard, the prior art now includes a so-called “sleep mode” of operation of the SRAM, which also is sometimes referred to with other terms such as “standby mode” or possibly still others. This mode is characterized as a period of time in which the data cells in the SRAM will not be accessed (i.e., either read or written), but the data state in each cell must be maintained because it is anticipated that eventually the operation of the SRAM will discontinue from the sleep mode, at which time the data previously stored therein will be needed; hence, there is a need to maintain the validity of that data during the sleep mode. With these considerations, the sleep mode typically is further characterized in that the voltage provided to the SRAM array of memory cells is reduced during the sleep mode as compared to the voltage supplied during all access operations. The reduction is typically to a level on the order of one-half of the voltage provided during data access operations of the SRAM, where the voltage applied to the SRAM array (often referred to as VDDA) during the data access operations is often set to a value referred to as VDD; thus, during the sleep mode, the voltage VDDA provided to the SRAM array is on the order of 0.5 VDD. In the prior art, the specific amount of reduction of VDDA, such as to a value of 0.5 VDD, is typically determined by the designer to accommodate worst case scenarios. For example, with the anticipated range of environmental and circuit conditions such as temperature, silicon variations, and the like, the reduced value of VDDA is fixed at a level to ensure that the data state is maintained in each SRAM array cell during the sleep mode, while also accommodating any change in the environmental and circuit conditions.
While the above-described approaches have proven workable in various implementations, the present inventors have observed that the prior art may be improved. Specifically, in connection with the present preferred embodiments, it has been observed that as the temperature to which an SRAM is exposed decreases, the amount of voltage required to maintain the data state in the SRAM cells increases. Thus, with the fixed-voltage levels in the standby mode of the prior art, the supply voltage for the standby mode is presumably established in contemplation of a worst-case scenario, that is, in respect to the voltage required at the lowest temperature anticipated to be experienced by the SRAM data cells (with whatever additional tolerance). However, the present inventors have recognized that when the SRAM is in standby mode and experiences higher temperatures, then the preestablished fixed voltage supply to the SRAM will necessarily cause a certain amount of current leakage across the SRAM array. Of course, current leakage is undesirable for various reasons, including increased power consumption and operational cost. Thus, the preferred embodiments as set forth below seek to improve upon the prior art as well as these associated drawbacks.